Magicians do their magic with smoke and mirrors. Computer architects do their magic with multiplexers.

A large part of ALU design is captured by the design of a 1-bit ALU. Then 1-bit ALUs can be combined to form a multi-bit ALU with a small amount of additional circuitry.

The diagram to the left captures the basic idea for a 1 bit ALU.


Each of the OPi boxes computes 1 bit for an operation. For example,

The multiplexer selects the output of the appropriate 1-bit operation. Its control input Op is derived from operation and function bits of a machine instruction.

ALUs typically can perform integer addition and subtraction. These operations require either some connections between 1-bit ALUs for carry propagation or additional carry lookahead circuitry. Subtraction also requires exclusive or gates inserted in front of one of inputs. The other input of the gate is connected to a subtract/add control signal.

ALUs can be designed to detect incorrect results due to limited word size. This requires a small amount of added circuitry in the high-order 1-bit ALU.

The basic idea for ALU design presented here is not suitable for complex operations such as multiplication, division, and floating-point operations. In modern processors these operations need to be split into multiple cycles to avoid long cycle times for all operations.

Dealing with multicycle operations requires some significant changes to the processor architecture. This is especially true with pipelining. The Register Renaming web page describes the organization used by modern processors.