The following web pages describe register renaming with a simplifying assumption: that there are no branch instructions. Modern processors that have a renaming architecture have a similar organization with significant enhancements in the instruction fetch circuitry and minor changes in the rest of the architecture. These changes support predicting whether or not conditional branches will be taken and speculative issue of instructions following the branches. With these changes CPI can be reduced to nearly 1.0.
Modern processors are also going beyond the architectural ideas presented here by issuing multiple instructions per cycle. This is called superscalar execution. For the most part, this uses the same basic architectural components, replicated to support parallel issue. Modern processors are currently capable of a CPI of about 0.4.