This presentation describes the implementation of integer addition and subtraction. Before discussing the implementation it is first necessary to understand the 2's complement representation of signed integers. This representation is used by all modern computers. At least a part of the reason is the fact that addition and subtraction work the same way for 2's complement signed numbers as for unsigned binary numbers.

Simple implementations for addition and subtraction use a ripple-carry adder. High performance implementations use Lookahead Carry.

The last topic to be considered is errors. Any implementation of addition and subtraction has the possibility of errors due to results too large to represent in a limited number of bits. The error indications are different for unsigned and signed numbers.

Signed and unsigned addition and subtraction can be implemented with relatively simple circuitry. This circuitry is slow due to ripple carry.

A full adder (labeled FA in the diagram below) is a logic circuit for performing one column of an addition. It has three inputs, two (X and Y below) for summand bits and one (Ci below) for a carry from the column to the right. Its outputs are a sum (S below) and carry (Co below) for the column to the left. This diagram shows 4 full adders connected to compute a 4-bit sum.

The 4-bit adder can easily be modified to do subtraction. Two changes are required to subtract Y from X. In effect, they do a 2's complement on Y

  • Invert all of the Y bits (do a 1's complement on Y).
  • Put a 1 into the low order Ci carry input (add 1).

By adding exclusive or (XOR) gates in front of the Y inputs to the full adders, the same circuitry can do either addition or subtraction as directed by a control signal S/A.

  • When S/A is 1 the circuitry subtracts Y from X.
  • When S/A is 0 the circuitry adds Y to X.

When two numbers are added or subtracted with the simple adder circuitry below, high-order bits of the sum are not ready until the carries have "rippled" from the low-order bits to the high order bits. Consider a 32-bit adder. Assuming full adders are implemented with 2-level logic, it takes 64 gate delays before the sum is ready. This is unacceptable for a modern high speed processor.

Error Indications

For adding unsigned numbers, a high-order carry out value of 1 indicates an error. It indicates that the summands could be represented in the available number of bits but the sum is too large.

For adding signed numbers, an error can only occur when the summands have the same sign. Then there is an error if the sum has the wrong sign, as indicated by its high-order bit.

Example 1

Consider the following addition of 8-bit integers.

  1 1         1 1
    1 1 0 0 0 0 0 1
    1 1 0 0 0 0 1 1
    1 0 0 0 0 1 0 0
      

If the bits represent unsigned numbers then the result is obviously in error — the sum is smaller than either of the summands. This error is indicated by the carry out from the high-order bit position (the leftmost blue 1).

On the other hand, if the bits represent signed numbers then the result is correct. You can only have an error if you add two numbers with the same sign and get a result with the opposite sign.

Example 2

Consider the following addition of 8-bit integers.

    1         1 1
    0 1 0 0 0 0 0 1
    0 1 0 0 0 0 1 1
    1 0 0 0 0 1 0 0
      

If the bits represent unsigned numbers then the result is correct. You only have an error if there is a carry out from the high-order bit position.

On the other hand, if the bits represent signed numbers then the result is obviously in error. Two numbers with the same sign are added and the result has the opposite sign.