The base case is a 1-bit comparator (blue dot).
Take four 1-bit comparators and connect their outputs into a
comparison combiner unit (green dot).
This gives you a 4-bit comparator.
Take four 4-bit comparators and connect their outputs into a
comparison combiner unit.
This gives you a 16-bit comparator.
Take four 16-bit comparators and connect their outputs into a
comparison combiner unit.
This gives you a 64-bit comparator.
An m -bit adder has two m -bit inputs, X and
Y and a 1-bit Ci (carry in) input.
It uses m modified full adders
The basic idea for lookahead carry generation is to use an augmented
comparator to generate all of the carry ins for the adders.
We will first look at how to get carry information from a comparison.
Then we will look at the overall structure of an m bit adder
and the modifications of the full adders needed to use lookahead carry.

The carry lookahead circuitry starts as a sum comparator.
Then circuitry is added for carry generation.
An m -bit sum comparator has two m -bit inputs X
and Y and two 1-bit outputs:

P (propagate) is 1 when the sum of the X and
Y inputs is equal to 1 _{m} and P is 0 when the
sum is less than 1 _{m} .
We do not care what the output is when the sum is greater than
1 _{m} — that is handled by the G output.
G (generate) is 1 when the sum of the X and
Y inputs is strictly greater than 1 _{m} , else
G is 0.
Like the ordinary comparator, we need to specify how to build a
4m -bit sum comparator from four m -bit sum comparators
and some additional circuitry, and we need to describe the base case
1-bit sum comparator.

Sum Comparator Reduction
For the sum comparator, we assume that we can build an m -bit
sum comparator.
From these building blocks we define how to build a 4m -bit sum
comparator.
The organization of the circuitry is the same as an ordinary comparator.
We just need to determine logic equations for the sum comparator
combiner unit.

P Output
What is the logic equation for the P output?

Answer
The sum of two 4m -bit numbers is equal to 1 _{4m}
precisely when each sum of their corresponding m -bit groups is
equal to 1 _{m} .

P = P3•P2•P1•P0

This has the same form as the ordinary comparator logic equation for EQ.
And it does not require computing any sums.

G Output
What is the logic equation for the G output?

Answer
The sum of two 4m -bit number X and Y is greater
than 1 _{4m} when the sum for any one of the
m -bit groups is greater than 1 _{m} and the sums
for the higher-order groups of X and Y are equal to
1 _{m} .

G = G3 + P3•G2 + P3•P2•G1 +
P3•P2•P1•G0

This has the same form as the ordinary comparator logic equation for GT.
Again, it does not require computing any sums.

Adder Structure
We can define an m -bit adder in a recursive manner similar to
an m -bit comparator.
In the reduction case, m > 1, it uses a modified
comparison combiner unit, which is called a carry lookahead unit.
The reduction is shown in the following diagram.

The EQ and GT inputs and outputs of the comparison combiner unit are
renamed to Ps and Gs, respectively, to reflect their role in lookahead
carry generation.
A carry lookahead unit also has carry outputs, C4, C3, C2, and C1, that
are ultimately fed back to the base case adders.
We need to develop the logic equations for these outputs.

Carry Outputs
We need to determine the logic equations for the carry outputs.

The C1 Output
What is the logic equation for C1 output?

Answer
A carry is needed into the second m -bit only if one of two
conditions is met.

The first adder generates a carry.
There is a carry into the first adder and it propagates through the
first adder.
C1 = G0 + P0 • C0

The Other Outputs
The logic equations for the other carry outputs are left as an exercise.

Full Adder Modifications
The base case 1-bit adder is a modified full adder.
Its carry output and associated circuitry are removed and replaced by
circuitry to generate outputs for base case comparison between X
and Y .
The logic equations can be obtained by substituting
Y for Y in the comparator base case
equations.

EQ is true when X = Y
EQ = X•Y +
X •Y

P is true when X = Y
P =
X•Y +
X •Y = X ⊕ Y

GT is true when X > Y
GT =
X•Y

G is true when X > Y
G = X•Y

If the carry lookahead circuitry is only used for carry lookahead and
not for comparison then can simplify the logic equation for P .
We can allow it to be 1 when X and Y are both 1.
This computes P with a simple OR gate.

P = X + Y

The justification for this change is that it does not affect P outputs
in the carry lookahead unit tree except when a corresponding G output is
1.
In effect, it allows carries to be incorrectly propagated, but only when
a carry would be generated anyway.

The full adders (FA ) are modified so that they generate P and G
outputs instead of a carry out.
Their X and Y inputs and their S output are not shown.
The P and G outputs of four 1-bit adders are connected into a carry
lookahead unit and the carry outputs of the carry lookahead unit are
connected back to the 1-bit adders.
This gives you a 4-bit adder as in the four full adders and the carry
lookahead unit at the upper right of the diagram.
The P and G outputs of four 4-bit adders are connected into a carry
lookahead unit and the carry outputs of the carry lookahead unit are
connected back to the 4-bit adders.
This gives you a 16-bit adder.