Book
Chapters
[B1] H. Tang, H. Zhang, A. Doboli, Towards High-Level
Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications - A
Case Study for a Sigma-Delta Analog-Digital Converter, Languages for
System Specification, Kluwer Academic
Publishers, pp. 201-216, ISBN:1-4020-7990-7, 2004.
Journal Papers (Supervised students are delineated with an asterisk (*))
[J10]
Peng Li*, Hua Tang, Design of a Low-Power
Coprocessor for Mid-Size Vocabulary Speech Recognition Systems, IEEE Transactions on Circuits and Systems I,
Vol. 58, No. 5, pp. 961-970, May 2011.
[J9]
M. Webb*, H. Tang, A Low-power and Low-complexity
Continuous-time Gm-C based Delta-Sigma Modulator for WCDMA/UMTS, International Journal of Electronics, Volume
96, Issue 6, pp. 585-602, Jun 2009.
[J8] M. Webb*, H. Tang, A Symbolic Approach toward High-level Variation-aware Topology
Synthesis of Delta-Sigma Modulators, International
Journal of Electronics, Volume 95, Issue 10, pp. 1033-1053, Oct.
2008.
[J7] H. Tang, A Systematic Design Flow for
Optimal Capacitance Assignment in Switched-Capacitor Biquads,
IEEE Transactions on Circuits and Systems I, Vol. 55, No. 7, pp. 2076-2087, Aug 2008.
[J4] H. Zhang, S. Doboli, H. Tang,
A. Doboli,
Compiled
Code Simulation of Analog and Mixed-Signal Systems Using Piecewise Linear
Modeling of Nonlinear Parameters, Integration the VLSI Journal, Elsevier,
Vol. 40, No. 3, pp. 193-208, Apr 2007.
[J3]
M. Webb*, H. Tang, Modeling Continuous-time Delta Sigma
Modulators in MATLAB SIMULINK for System-level Simulation and Specification
Translation, WSEAS Transactions on
Circuits and Systems, Issue 12, Vol. 5, pp. 1760-1767, Dec 2006 (Invited
paper).
[J2] H. Tang, H. Zhang, A. Doboli, Refinement
based Synthesis of Continuous-Time Analog Filters Through Successive Domain
Pruning, Plateau Search and Adaptive Sampling, IEEE Transactions
on Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 8, Aug 2006, pp. 1421-1440.
[J1] H. Tang, A. Doboli, High-level Topology Synthesis for Delta-Sigma
Modulators Optimized for Complexity, Sensitivity and Power Consumption,
IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, Vol. 25, No. 3, March 2006, pp. 597-607.
Conference Papers (Supervised students are delineated with an asterisk (*))
[C27] H. Dinh*, H.
Tang, E. Kwon, Camera Calibration
for Roundabout Traffic Scenes, poster presented in Transportation Research Board Annual Meeting, Washington DC, Jan
23-27th, 2011, 13 pages.
[C26] H. Tang, An Optimization Based Approach for Topology Exploration of Switched-Capacitor
Biquad Filters, Proc. of Intelligent Human Machine Systems and Cybernetics Conference
(IHMSC¡¯10), Nanjing, China, Aug 26-28th, 2010, pp. 307-310.
[C25] P. Li*, H. Tang, A Low-power VLSI Implementation for Full-search Variable Block Size
Motion Estimation in H.264/AVC, Proc.
of IEEE International Symposium on Circuits and Systems (ISCAS¡¯10), Paris,
France, May 30-Jun 2nd, 2010, pp. 2972-2975.
[C24] P. Li*,
H. Tang, VLSI Architecture Design for Reconfigurable Block Size Motion
Estimation, Proc. of IEEE
International Conference on Consumer Electronics (ICCE¡¯10), Las Vegas, NV,
Jan 11-13rd, 2010, pp. 439-440.
[C23] P.
Li*, H. Tang, Design of a
Co-Processor for Output Probability Calculation in Speech Recognition, Proc. of IEEE
International Symposium on Circuits and Systems (ISCAS¡¯09), Taipei, Taiwan,
May 24-27th, 2009, pp. 369-372.
[C22]
P. Li*, H. Tang, Q. Lian, Low Power
Embedded Speech Recognition System Based on a MCU and a Co-processor, Proc. of 34th IEEE International Conference
on Acoustics, Speech, and Signal Processing (ICASSP¡¯09), Taipei, Taiwan,
April 19-24th, 2009, pp. 625-628.
[C21] H. Chang*,
H. Tang, Efficient System-level Statistical Design of Analog Systems via
Variance Minimization, Proc. of
IASTED International Conference on Circuits and Systems, Kona, HI, August
18-20th, 2008, pp. 1-6.
[C20] Y. Zheng*, H.
Tang, Towards a Hardware-based
System for Real-Time Vehicle Tracking, Proc.
of IEEE Intelligent Vehicle Symposium (IV¡¯08), June 4-6th, Eindhoven,
Netherlands, 2008, pp. 285-290.
[C19] H. Chang*,
H. Tang, A Simple Technique to Reduce Clock Jitter Effects in Continuous-time
Delta-Sigma Modulators, Proc. of IEEE
International Symposium on Circuits and Systems (ISCAS¡¯08), Seattle, WA,
May 23-26th, 2008, pp. 1870-1873.
[C18] M. Webb*,
H. Tang, Analog Design Retargeting by Design Knowledge Reuse and Circuit
Synthesis, Proc. of IEEE
International Symposium on Circuits and Systems (ISCAS¡¯08), Seattle, WA,
May 23-26th, 2008, pp. 892-895.
[C17] H. Tang, Post-Optimization of Delta-Sigma Modulators Considering Circuit
Non-idealities, Proc. of IEEE
International Symposium on Circuits and Systems (ISCAS¡¯08), Seattle, WA,
May 23-26th, 2008, pp. 2546-2549.
[C16] H. Tang, Hierarchical Statistical Analysis of Performance Variation for
Continuous-time Delta-Sigma Modulators, Proc.
of 15th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC¡¯07), Atlanta, GA, Oct 15-18th, 2007, pp. 37-41.
[C15] H. Tang, T. Kwon, Y. Zheng*, H. Chang*, Designing CMOS Processors for Vehicle
Tracking, Proc. of 50th IEEE
International Midwest Symposium on Circuits and Systems (MWSCAS¡¯07),
Montreal, Canada, Aug 5-8th, 2007, pp. 1328-1331.
[C14] H. Tang, M. Webb*, Optimal Synthesis of Delta-Sigma Modulator
Topologies Considering SNR Variation, Proc.
of 50th IEEE International Midwest Symposium on Circuits and Systems
(MWSCAS¡¯07), Montreal, Canada, Aug 5-8th, 2007, pp. 730-733.
[C13] M. Webb*,
H. Tang, System-level Simulation for Continuous-Time Delta-Sigma Modulator in
MATLAB SIMULINK, Proc. of 5th WSEAS
International Conference on Circuits, Systems, Electronics, Control &
Signal Processing (CSECS'06), Dallas, TX, Nov 1-3rd, 2006,
pp. 1-4 (Invited paper).
[C12] Y. Wei, H. Tang, A. Doboli, Systematic Methodology for
Designing Reconfigurable Delta Sigma Modulator Topologies for Multimode
Communication Systems, Proc.
of IEEE Design Automation and Test in Europe Conference (DATE'06), Messe Munich, Germany,
March 6-10th, 2006, pp. 1-6.
[C11] H. Tang, H. Zhang, A. Doboli, Layout
Aware Analog Synthesis based on Multi-level Optimization, Performance Model
Approximation, and Solution Space Pruning, Proc. of SINTES12
(International Symposium on System Theory, Automation, Robotics, Computers,
Electronics, and Instrumentation), Craiova, Romania, Oct 20-22nd, 2005, pp.
1-4.
[C10] H. Tang, H. Zhang, A. Doboli, Parameter Domain
Pruning for Improving Convergence of Synthesis Algorithms, Proc. of IEEE
International Symposium on Circuits and Systems (ISCAS'05), Kobe, Japan,
May 23-26th, 2005, pp. 1282-1285, Vol. 2.
[C9] H. Zhang, H. Tang, A. Doboli, An
Explorative Tile-based Tool for Automated Design, Placement and Routing of High
Frequency Analog Filters, Proc. of IEEE International Symposium on
Circuits and Systems (ISCAS'05), Kobe, Japan, May 23-26th, 2005, pp.
5629-5632, Vol. 6.
[C8] H. Tang, A. Doboli, MINLP Based
Topology Synthesis for Delta-Sigma Modulators Optimized for Signal Path
Complexity, Sensitivity and Power Consumption, Proc. of IEEE Design,
Automation and Test in Europe Conference (DATE'05), Messe
Munich, Germany, Mar 7-11th, 2005, pp. 264-269.
[C7] H. Tang, H. Zhang, A. Doboli, Towards High-Level Synthesis of Analog and
Mixed-Signal Systems from VHDL-AMS Specifications - A Case Study for a
Sigma-Delta Analog-Digital Converter, Proc. of Forum on Specification
and Design Languages (FDL'03), Frankfurt, Germany, Sep 23-26th, 2003, pp.
1-11.
[C6] N. Thepaysuwan,
H. Tang, A. Doboli, An Exploration Based
Binding and Scheduling Technique for Synthesis of Digital Blocks for
Mixed-Signal Applications, Proc. of IEEE International Symposium on
Circuits and Systems (ISCAS'03), Bangkok, Thailand, May 25-28th, 2003, pp.
629-632, Vol. 5.
[C5] H. Tang, H. Zhang, A. Doboli, Synthesis of Continuous-Time Filters and Analog
to Digital Converters by Integrated Constraint Transformation, Floorplanning and Routing, Proc. of ACM Great Lakes
Symposium on VLSI (GLSVLSI'03), Washington DC, Apr 28-29th, 2003, pp.
207-210.
[C4] H. Tang, H. Zhang, A. Doboli, Layout-Aware Analog System Synthesis Based on
Symbolic Layout Description and Combined Block Parameter Exploration, Placement
and Routing, Proc. of IEEE Computer Society Annual Symposium on VLSI
(ISVLSI'03), Tampa, FL, Feb 20-21st, 2003, pp. 266-271.
[C3] H. Tang, A. Doboli, Layout-Aware Synthesis for Analog Systems Based
on Combined Block Sizing, Floorplanning and Global
Routing, poster paper, IEEE Annual International ASIC/SOC Conference,
Rochester, NY, Sep 25-27th, 2002.
[C2] H. Tang, A. Doboli, Employing Layout Templates for Synthesis of
Analog Systems, Proc. of IEEE International Midwest Symposium on Circuits
and Systems, Tulsa, OK, August 6-8th, 2002, pp 505-508, Vol. 2.
[C1] H. Tang, A. Doboli, Layout Aware
Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing, Proc. of IEEE
International Workshop on Logic and Synthesis (IWLS), New Orleans, LA, Jun
4-7th, 2002, pp. 41-44.
PhD Forum Presentation:
An Efficient Methodology and Algorithm for
Synthesis and Optimization of Analog and Mixed-signal Systems, Ph.D. thesis
presented at 2005 3rd EDAA PhD Forum (joint with Design, Automation and
Test in Europe Conference (DATE'05)), Messe
Munich, Germany, Mar 7-11th, 2005.