Due: 23 October 2002

1. Text 4.2 and Text 4.3 as a combination. Tabulate your results and for each case, draw a diagram of the transistor with the bias voltages carefully labeled with the correct sign. When you tabulate your results, list whether each of the two junctions is either reverse or forward biased.

2. Text 4.8. You can and should ignore the leakage current. Partial answers include I_C = 8.61 mA and for Part b, you will show saturation with I_C = 5.25 mA. Besides the analytical solution, verify your results with a SPICE simulation. Justify that the SPICE default npn has specifications close to the specifications listed in the problem. To obtain this Q-Point information, look at the output file generated with the .OP command (which may or may not be a default operation in your version of SPICE).

3. Text 4.19 NPN Q-Point Analysis. Label your voltages and currents carefully on the circuit diagram. In addition, sketch and label a small-signal model for this circuit using the hybrid-pi BJT device model. Model values must be computed.

4. Text 4.20 PNP Q-Point Analysis. Label your voltages and currents carefully on the circuit diagram. In addition, sketch and label a small-signal model for this circuit using the hybrid-pi BJT device model. Model values must be computed.

If you want additional practice, I used this problem on an old quiz. I will not collect this problem. Obtain/derive the design equations you would use to establish the Q-Point values for V_CEQ, I_CQ, and I_BQ. Observe that the circuit is being operated using two dc power supplies of +V_CC and -V_EE. Assume b >>1 and operation in the forward active region.. Sketch and label all key points of the dc load line on a general set of i_C versus v_CEaxes.

v_CE

As you go out into the real-working-world, you will attend lots, and I mean lots of meetings. Most have zero or even negative outcomes and utility. I have little doubt you will find this useful.