ECE 2212
PROBLEM SET 11
S. G. Burns
Due: Wednesday, 24 April 2013
Study selected portions
of text Sections 16.2 through 16.5 related to basic and Widlar
BJT Current Mirrors and MOS-based current sources as well as the class
discussions we started on Monday, 15 April. The Laboratory Experiment from Thursday, 18
April, should help. Quiz 11 will not cover the Emitter-Coupled
Pair that we will start on Monday, 22 April.
1. Simple and Widlar Current Sink and
Source Calculations
(a)
Compute a value
for IC2 which is the current you would sink from a circuit requiring
that current bias level.
(b)
Design a pnp circuit based upon the npn circuit
shown in Figure 1 that would operate as a current source, rather than a current
sink, for the current computed in Part (a). Your design must include a
well-labeled circuit diagram.
(c)
Design a Widlar current source to sink the current computed in Part
(a). Refer to Figure 2. You have a fair amount of flexibility in R1 and R2.
Follow guidelines presented in Monday’s and Wednesday’s ,
15 and 17 April, class discussion.
2. Combine the ideas from Problem 1 to
design a current source/sink mirror system that provides 0.5 mA, 1.0 mA, and 50 μA as shown in the diagram below. The idea is that
your circuit design can directly replace the three current source symbols shown
in the diagram.
(a)
You are to use only
one reference resistor.
(b)
You will need to
use npn and pnp transistors.
(c)
Different
transistor cross-sectional areas are allowed within the constraints of IC
design and reasonableness.
(d)
Assume β
>> 1 for all transistors.
(e)
Assume room
temperature operation.
(f)
You should use
both basic and Widlar configurations as appropriate.
(g)
Your design and
analysis must show all relevant design equations and assumptions.
(h)
Your design must
include a detailed and accurately labeled circuit diagram.
3. The following is a circuit diagram of a
National Semiconductor LM 741 operational amplifier. Recall from the beginning
of the semester that you will be able to analyze key sub-circuits of
operational amplifiers and related circuits by the end of the course. I have circled key elements of the current source
system you are analyze. Assume all |VBE(on)|
= 0.7 volts. V+ = 12 volts and V- = -12 volts. All npn transistors have equal
junction areas and all pnp transistors have equal
junction areas. The Fairchild μA 741 diagram on
text page 1097, Figure 16.46, is another variation. I prefer to use the
National Semiconductor LM 741 circuit diagram and Signetics
μA 741 circuit diagram because they are a bit
easier to read. There are differences in some component values because they
originate from different manufacturers.
I suggest studying the example in Section 16.9.2.
Compute values for IREF, IC10, and I13.
4. Text 16.8 Parts (b) and (c) only. Do not
do the case for a non-zero λ.
This is an NMOS current mirror system.
5. NMOS
Current Mirror System.
Once you realize that ID2 = 50 μA
the problem can be done by inspection or at most, on one line without a calculator! Several elements of this problem were used on
an old quiz.
Assume
the following:
(a)
M1 and M2 are matched (b) l
= 0 for all MOSFETS (c) L identical for all FETS. (d) ID2 = 50 μA.
(e)
W1=W2=W3=W6=W8 (f) W4=W5=2 x W2 (g) W7 = 3 x W8 (h) Except for W/L ratios, the
fabrication process are the same for all FETs.
Pay
attention to sign conventions!
Provide
values for:
ID3
=__________________ ID4 = ____________________ ID7 ________________
ID5
= _________________ (Trick question. Careful-look at the
drain circuit for M5!)