Homework P&H Ch. 5

Answer the following questions about Patterson and Hennessy, Chapter 5. You only need to turn in those that have a point count assigned.

  1. (1 point) A cache has a 95% hit rate. The access time to its local store is 4 ns. The access time to the lower level store is 60 ns. What is the effective access time?
  2. What are the options for handling writes ito a cache?
  3. (1 point) A computer has a 8-way associative 128 KByte cache. Each cache block is 16 bytes. The addresses from the processor are 32-bit byte addresses. How many bits are in the tag, set, and offset fields of a memory address?
  4. (1 point) What is the most important consideration in the design of a virtual memory system?
  5. (2 points) Describe how virtual addresses are translated into physical addresses in a paged virtual memory system.
  6. If nothing was done about it, every instruction fetch, load, or store would result in two memory accesses, one for the page table entry and then one for the instruction or memory data. How do processors avoid the most of the extra page table entry accesses?
  7. How does a processor recognize page faults? What does a processor do one occurs?