Review for Midterm 1

1. What three factors determine the performance of a computer?
2. What is the best possible CPI that the MIPS architecture can acheive without pipelining? With pipelining?
3. What are the most important changes required to implement pipelining?
4. What are structural hazards? How can they be eliminated? Give examples.
5. In a pipelined architecture, the hardware needs to fetch an instruction on every cycle. It also needs to access memory for loads and stores. What is usually done to keep the multiple accesses from causing a stall?
6. What kinds of potential data hazards are contained in the following MIPS code? If the processor does not do register forwarding, which ones require stalls? What if register forwarding is used? For your answers, assume a pipeline similar to the MIPS pipeline described in the text, and assume that the execution phase is always accomplished in a single cycle.

       add.d	$f2, $f4, $f8
       mul.d	$f4, $f6, $f2
       sub.d	$f2, $f4, $f6
   

7. What is forwarding? How does it improve performance?
8. In the MIPS pipeline, register forwarding can eliminate stalls due to a data dependence between two successive arithmetic instructions, but not due to a data dependence between a load and a successive arithmetic instruction. Why is there a difference?
9. What is a control hazard?
10. What is a delayed branch? How does it improve performance?
11. What does the phrase precise exceptions mean?
12. What are some problems that arise when some instructions require more than one cycle for execution?
13. Complete the following register renaming table.

    Instruction	$f8	$f10	$f12	Renamed Instruction
    initial	V0	V1	V2	---------------------
    l.s $f10, 0($5)
    l.s $f12, 0($6)
    mul.s $f10, $f10, $f12
    add.s $f8, $f8, $f10

14. What is accomplished by the renaming process?
15. In a register renaming architecture, what is the purpose of reservation stations?
16. In a register renaming architecture, what conditions must be met before execution begins for an instruction?
17. What happens during the commit phase in a register renaming architecture?
18. In a register renaming architecture, what conditions must be met before an instruction is committed?
19. Suppose you have a register renaming processor and that its branch prediction is always right. Suppose it never needs to stall due to a lack of available reservation station slots or functional units. Why might it still fail to complete one instruction per cycle?
20. What does speculative execution mean? Why would you want to do it?
21. What is the purpose of a branch-history table? What kind of values does it hold? What kind of data is used as a lookup key?
22. What is a branch-target table? What kind of values does it hold? What kind of data is used as a lookup key?
23. What is superscalar pipelining?
24. What does multithreading mean in the context of computer architecture?
25. Discuss some ways that the instruction set can make pipelining difficult.