These diagrams are broken up into the following sections.

• Datapath
• Basic Combinational
• Multiplexer
• Full Adder
• State
• Shifting
• Arithmetic
• ALU

All URL hashes refer to the web page http://www.d.umn.edu/~gshute/logic/SVG.html.

Datapath: #datapath

AND Gate: #and

AND Gate As a Control: #and-ctrl

OR Gate: #or

XOR Gate: #xor

XOR Gate As a Control: #xor-ctrl

Multiplexer: #multiplexer

Multiplexer Implementation: #mux-imp

Demultiplexer Implementation: #demux-imp

Full Adder: #full-adder

Full Adder Implementation: #full-adder-imp

Carry Lookahead Full Adder: #cla-fa

Carry Lookahead Full Adder Implementation: #cla-fa-imp

Flip-Flop: #flip-flop

SR Latch Implementation: #sr-latch-imp

Clock Pulser: #clock-pulser

Flip-Flop Implementation: #flip-flop-imp

Register Implementation: #register-imp

A 1-Bit ALU: #alu

A 1-Bit ALU Implementation: #alu-imp

Carry Lookahead ALU Implementation: #cla-alu-imp

A 4-Bit Adder: #4-adder

A 4-Bit Adder-Subtracter: #4-adder-subtracter

A 4m-Bit Adder: #4m-adder

A Comparator: #comparator

A 4m-Bit Comparator: #4m-comparator

Hierarchical Trees - #hierarchical-trees

A 16-Bit Carry Lookahead ALU - #16-alu

A 16-Bit Adder - #16-adder

Shifting - #shifting

Shift Register - #shift-register-imp

Barrel Shifter - #barrel-shifter-imp

Multiplier Divider - #multiplier-divider