A carry-lookahead adder replaces ripple carry generation with lookahead carry generation. Lookahead carry generation is based on a hierarchical arrangement of carry lookahead units. Before describing a carry-lookahead adder it is useful to look at a simpler hierarchical circuit for a comparator.

#### A Hierarchical Comparator

An m-bit comparator has two m-bit inputs, X and Y. It has two 1-bit outputs:

• EQ is 1 when the X and Y inputs are equal.
• GT is 1 when the X input is greater than the Y input.

A hierarchical circuit is defined recursively. For a hierarchical comparator, we assume that we can build an m-bit comparator. From 4 m-bit comparators and some additional circuitry we define how to build a 4m-bit comparator.

Like any recursion, we need to specify how to reduce a larger problem to smaller ones (describe the interconnections and the additional circuitry) and define a base case (a 1-bit comparator) that terminates the recursion.

#### Comparator Reduction

The 4m-bit comparator has 4m-bit inputs, X and Y. We can split these into four m-bit groups:

• X3 and Y3 (the high-order m bits),
• X2 and Y2,
• X1 and Y1, and
• X0 and Y0 (the low-order m bits).

We route the Xis and the Yis into separate m-bit comparators and introduce a circuit block to combine their results:

Before proceeding to the base case, we need to figure out the logic equations for the combiner.

#### Comparator Base Case

The base case 1-bit comparator has 1-bit inputs, X and Y. We need to generate the EQ and GT outputs.

#### The EQ Output

What is the logic equation for the EQ output?

1-bit numbers X and Y are equal when both are 1 or both are 0.

EQ = X•Y + XY = X ⊕ Y

#### The GT Output

What is the logic equation for the GT output?

The 1-bit number X is greater than the 1-bit number X only when X is 1 and Y is 0.

GT = X•Y

#### Note

To compare signed numbers the only thing that needs to change is the 1-bit comparator GT output for the high-order (sign) bit:

GT = X•Y

#### Getting Carry Information From a Comparison

Suppose we are adding two m-bit numbers X and Y. Generally X and Y may be corresponding groups of bits from larger numbers. We would like to be able to to determine the effects of adding X and Y on carries in the larger numbers. Let 1m denote the m-bit number whose bits are all 1. This number is critical for determining the effects on carries:

• X + Y > 1m:

The group generates a carry. There is always a carry out even if there is no carry in.

• X + Y = 1m:

The group propagates a carry. There is a carry out only if there is a carry in.

• X + Y < 1m:

The group cannot have a carry out, even if there is a carry in.

That is, we can get carry information from a comparison between X + Y and 1m. But we still have an addition which involves carries, so this observation has not yet helped us.

#### Getting Carry Information From a Comparison

Suppose we try subtracting Y from both numbers to be compared. That is,

• instead of comparing X + Y and 1m
• we compare X and 1m - Y.

At first glance this only appears to convert the problem from an addition with carries into a subtraction with borrows. However, when you subtract an m-bit number from 1m you never get any borrows. In fact 1m - Y is just Y, the bitwise complement of Y.

#### Getting Carry Information From a Comparison

So here is how we get carry information from a comparison. X and Y denote m-bits numbers, generally corresponding groups of bits from larger numbers, and Y denotes the bitwise complement of Y.

• X > Y:

The group generates a carry. There is always a carry out even if there is no carry in.

• X = Y:

The group propagates a carry. There is a carry out only if there is a carry in.

• X < Y:

The group cannot have a carry out, even if there is a carry in.

#### The Sum Comparator

The carry lookahead circuitry starts as a sum comparator. Then circuitry is added for carry generation. An m-bit sum comparator has two m-bit inputs X and Y and two 1-bit outputs:

• P (propagate) is 1 when the sum of the X and Y inputs is equal to 1m and P is 0 when the sum is less than 1m. We do not care what the output is when the sum is greater than 1m — that is handled by the G output.
• G (generate) is 1 when the sum of the X and Y inputs is strictly greater than 1m, else G is 0.

Like the ordinary comparator, we need to specify how to build a 4m-bit sum comparator from four m-bit sum comparators and some additional circuitry, and we need to describe the base case 1-bit sum comparator.

#### Sum Comparator Reduction

For the sum comparator, we assume that we can build an m-bit sum comparator. From these building blocks we define how to build a 4m-bit sum comparator. The organization of the circuitry is the same as an ordinary comparator. We just need to determine logic equations for the sum comparator combiner unit.

#### P Output

What is the logic equation for the P output?

The sum of two 4m-bit numbers is equal to 14m precisely when each sum of their corresponding m-bit groups is equal to 1m.

P = P3•P2•P1•P0

This has the same form as the ordinary comparator logic equation for EQ. And it does not require computing any sums.

#### G Output

What is the logic equation for the G output?

The sum of two 4m-bit number X and Y is greater than 14m when the sum for any one of the m-bit groups is greater than 1m and the sums for the higher-order groups of X and Y are equal to 1m.

G = G3 + P3•G2 + P3•P2•G1 + P3•P2•P1•G0

This has the same form as the ordinary comparator logic equation for GT. Again, it does not require computing any sums.

We can define an m-bit adder in a recursive manner similar to an m-bit comparator. In the reduction case, m > 1, it uses a modified comparison combiner unit, which is called a carry lookahead unit. The reduction is shown in the following diagram.

The EQ and GT inputs and outputs of the comparison combiner unit are renamed to Ps and Gs, respectively, to reflect their role in lookahead carry generation. A carry lookahead unit also has carry outputs, C4, C3, C2, and C1, that are ultimately fed back to the base case adders. We need to develop the logic equations for these outputs.

#### Performance Improvement

• All 1-bit adder P and G outputs are ready after 1 gate delay.
• The carry lookahead unit outputs are ready after 2 more gate delays. Some of these outputs are fed into the 1-bit adder Ci inputs.
• The 1-bit adder S outputs are ready after 2 more gate delays.