All MIPS instructions are 32 bits, or 4 bytes, long. The fixed length is almost universal in RISC processors. The 32-bit size is currently the most common size. This could change in a few years.

When MIPS instructions are classified according to coding format, they fall into four categories: R-type, I-type, J-type, and coprocessor. These formats are closely related to the execution activities in the processor circuitry.

The coprocessor coding format is not described here. Although the use of a coprocessor is advantageous for an embedded processor, desktop and server processors have not used them for about 20 years.

Many MAL instructions get expanded into 2 or 3 MIPS instructions. These expansions are often used to deal with immediate operands and idiosyncracies of the MIPS instruction set. Some of these expansions use $at as a temporary register.

MIPS assemblers normally make the following expansions. For some instructions more than one expansion may be applied. There are other expansions that are not described here.

• When imm cannot be represented as a 16-bit number

      li reg, imm
            

  is expanded to

      lui reg, imm[31:16]
      ori reg, reg, imm[15:0]

•     move reg1, reg2
            

  is expanded to

      or reg1, reg2, $0

•     la reg, label
            

  is expanded to

      li reg, labelAddress
            

•     load or store reg, label
            

  is expanded to

      la $at, label
      load or store reg, 0($at)

• op reg1, reg2, imm
            

  is expanded to

      li $at, imm
      op reg1, reg2, $at

Instruction execution involves the following activities, which are approximately in order. The program counter (PC) hold the address of the next instruction. The arithmetic-logic unit (ALU) performs arithmetic and logical operations such as adds and subtracts. The ALU is designed to combine two source operands to produce a result.

• Instruction fetch
  The instruction is fetched at the address specified by the PC.

• Program counter (PC) update
  A new value for the PC is computed in preparation for fetching the next instruction. Part of the update, computing the address of the following instruction, is done automatically. For branches and jumps, this value is later updated under the direction of control signals.

• Instruction decode
  Control signals are generated to implement the instruction.

• Source operand fetch
  Possible ALU operands are fetched from the register set and the immediate field of the instruction.

• Arithmetic-logic unit (ALU) operation
  A control signal selects the second operand for the ALU from either the second register read port or the immediate field of the instruction. A control signal directs the ALU to perform an appropriate operation for the instruction.

• Memory read
  The memory address is computed in the ALU. A control signal directs memory to read data. A control signal selects memory read data as the data to be written to the destination register. A control signal selects rt as the destination register. A control signal enables a write to the destination register.

• Memory write
  The memory address is computed in the ALU. The data to be written comes from the second read port of the register set. A control signal directs memory to write data.

• Register write
  A control signal selects the destination register. A control signal selects the ALU output as the data to be written. A control signal directs the destination register to write the data.