MIPS Single-Cycle Processor Implementation

Two versions of the single-cycle processor implementation for MIPS are given in Patterson and Hennessey. The first, Figure 4.17, shows an implementation that omits the jump (j) instruction. The second, Figure 4.24, includes the jump instruction.

In order to understand these figures it is necessary to understand four things.

There are two kinds of logic circuitry: combinational logic and state elements. State elements retain information for the duration of a CPU cycle. During the clock cycle combinational logic generates new values for the state elements. These values are not captured by the state elements until the end of a cycle.

Combinational logic

State Elements

Clock Time

The clock time, one of the three factors in the performance equation, is set to be greater than the combinational gate delays plus any setup time required for state elements. The setup time is usually small compared to the combinational gate delays.

The control signals are grouped according to the following instruction execution activities.

A read control signal is sent to memory. The contents of the program counter (PC) are used as an address. Instruction fetch is the same for all instructions.

Control Signals

Instruction fetch is automatic, requiring no control signals.

The PC gets a new value selected from the following.

The most general way of implementing PC update is to have a PC source multiplexer with one input for each possible next PC value in the above list.

PC update may be done in more than one step in a multicycle implementation or a pipelined implementation. Then the processor typically does a simple increment (PC ← PC + 4) automatically, then make later modifications for branches, jumps, and interrupts.

Control Signals

The following are the control signals given in Patterson and Hennessey.

In the general implementation described above, the multiplexer control is a multibit signal with a value for each of the possible PC source values.

Instruction decoding produces controls signals for the datapath and memory. The inputs to control circuitry are the opcode and function fields of the instruction. It generates the following kinds of control signals.

Instruction decode is the same for all instructions.

Control Signals

Instruction decode is automatic, requiring no control signals.

The ALU is designed to combine two source operands to produce a result. The source operand fetch activity fetches the two source operands. One source operand is always specified by the rs instruction field. The other is selected from the following.

Control Signals

For most instructions the ALU performs the operation suggested by the instruction mnemonic, which is coded into either the opcode or the function instruction field. For loads and stores the ALU computes the address, adding the sign extended immediate field of the instruction to the contents of the register specified by the rs field of the instruction. For branches the ALU can do a subtraction in order to compare two source operands, using the result to determine whether or not to do further a further update of the PC.

Control Signals

A read or write control signal is sent to memory. The result from the ALU is used as an address.

Control Signals

Some instructions, such as branches, jumps, and stores, do not write to a register. For the instructions that do write to a register, the destination register can be one of the following.

The value to be written to the register can come from the following places.

Control Signals