This web presentation is a top-down introduction to the MIPS Single-Cycle Datapath/Control diagram (the fifth menu item to the left). It is roughly a combination of Figures 4.17 and 4.24 in Patterson and Hennessey. This diagram is also available as a PDF document here.

Before looking at the diagram we need a little bit of context:

• A very brief introduction to logic circuits.
• A very high-level view of processor's datapath.
• A quick overview of some intermediate-level processor organizations. The single-cycle organization is one of these organizations.

After looking at the diagram we will:

• Look at black-box descriptions of the components of the diagram.
• Take a quick look at the functions of control signals in the diagram.

Organizations

There are four major processor organizations:

• Single-cycle organization
  This is the organization described in this web presentation. It is characterized by the fact that each instruction is executed in a single clock cycle. It is not a realistic implementation — it requires two separate memories: one for data and one for instructions. Also, the clock cycle has to be made quite long in order for all of the signals generated in a cycle to reach stable values.
• Multicycle organization
  This organization uses multiple clock cycles for executing each instruction. Each cycle does only a small part of the work required so the cycles are much shorter. Much of the circuitry is the same as the single-cycle implementation. However, more state components must be added to hold data that is generated in an early cycle but used in a later cycle. See MIPS Multicycle Implementation.
• Pipelined organization
  Like the multicycle organization, the pipelined organization uses multiple clock cycles for executing each instruction. By adding more state components for passing data and control signals between cycles, the pipelined organization turns the circuitry into an assembly line. After the first cycle of one instruction has completed you can start the execution of another instruction, while the first moves to its next cycle. Several instructions can be in different phases of execution at the same time. See Pipelining.
• Register renaming organization
  Register renaming is an extension of the pipelining idea. It deals with the data dependence problem for a pipeline — the fact that instructions in the pipeline produce data needed by other instructions in the pipeline. See Register Renaming.

MIPS Single-Cycle Datapath and Control

Diagram Components

There are two basic types of logic components: combinational components and state components.

• A combinational component behaves like a simple function. Its outputs depend only on the current values of its inputs.
• A state component behaves more like an object method. Its output also depends on the past history of its inputs.

Combinational Components

The following are the combinational components in the diagram.

• Multiplexers
• Sign Ext
• Adder
• ALU
• Control
• ALU Control
• PC Update Control

Multiplexers

A multiplexer is a logic component with multiple data inputs (X and Y), a single control input (Sel), and a single output (Out). At any time its output is the same as one of its inputs. Which one is determined by the control input.

Input and Output Size

The number of bits in the output signal can in principle be any number. Each data input has the same number of bits.

Inputs and Control

A multiplexer can in principle have any number of data inputs. The control signal has as many bits as needed for the selection. One bit suffices for just 2 data inputs, 2 bits suffices for 3 or 4 data inputs, and 3 bits suffices for 5 to 8 data inputs.

MIPS Single-Cycle Diagram

The three multiplexers in the MIPS diagram all have just two 32-bit data inputs and their outputs are the same size. Since they have only two data inputs, their control inputs are just one bit.

Sign Ext

The Sign Ext component performs sign extension, converting a 16-bit 2's complement number to a 32-bit 2's complement number. The low-order 16 bits of the output are the same as the input. The high-order 16 bits of the output are all copies of the sign (high-order) bit of the input.

Adder

An adder just performs binary addition of its two inputs to produce a sum output.

ALU

The ALU (Arithmetic-Logic Unit) can perform a number of different operations, combining its two data inputs (X and Y) into a single primary output (Out). Typical operations include additions, subtractions, and bitwise logical operations.

The ALU also has a secondary output (cc) that encodes a comparison of its inputs. It is a 2-bit signal. One bit is true when X = Y, the other when X > Y. The cc output is only valid when the ALU is directed to do a subtraction.

Operation Control

The operation performed by the ALU is determined by a control signal (Op). For comparisons the control signal usually directs the ALU to do a subtraction.

Control

The (main) control component uses the opcode field of the instruction to generate most of the control signals.

ALU Control

All op bits for an R-type instruction are 0. The operation is encoded into the fn bits. For R-type instructions, the main Control component delegates the determination of the ALU operation to the ALU Control.

Operation Control

For non-R-type instructions, the ALU Control just passes the ALUOp control from the main Control to the ALU. For R-type instructions the main Control sends a special code to the ALU Control. This code directs the ALU Control to use the fn bits to determine the operation.

PC Update Control

The PC Update Control component handles program counter update as directed by a Branch control signal and a comparison code (CC) signal from the ALU. It selects among addresses constructed from the incremented PC (PC+4), the instruction imm field, and the instruction targ field.

MIPS Single-Cycle Diagram

In Figure 4.17 of Patterson and Hennessey, the Branch control signal is a single bit. The comparison code is also a single bit: the zero output of the ALU, which indicates equality when the ALU is directed to subtract. The implementation in Figure 4.17 only supports a branch on equality and no jumps.

In Figure 4.24 of Patterson and Hennessey, jumps are supported by adding a Jump control signal. We can view this as converting the Branch signal into a 2-bit signal, though perhaps it should be renamed.

Supporting a variety of branch conditions requires additional information from the ALU about the comparison and additional Branch control bits to indicate when branching should occur.

State Components

The following are the state components in the diagram.

• The Program Counter (PC)
• Registers
• Instruction Memory
• Data Memory

All of these components except the PC contain multiple words of data organized like an array. The analog to an array index is either a register number or a memory address. It is used to select words to be either read through read ports or written through write ports.

The Program Counter (PC)

The PC is just a simple 32-bit register. Its output (pc) is used as the address for Instruction Memory. It also feeds into an adder to generate the default pc+4 value address of the next instruction. This is one of the several inputs to the PC Update Control that it uses to generate its newpc output.

Program Counter Update

When the clock (not shown) starts a new cycle pc changes to match the newpc input. The newpc input is generated by the PC Update Control circuitry.

Registers

The Registers component is a register bank — a component that contains multiple registers and provides read and write access to them.

In the MIPS processor there are 32 registers in the Registers component. Each register consists of 32 flip-flops, each storing 1 bit of data. In addition the component contains two read ports and one write port.

Read Ports

The input signal RdReg1 and the output signal RdData1 make up the first read port. The input signal RdReg2 and the output signal RdData2 make up the second read port.

• The input signals, RdReg1 and RdReg2, are 5-bit signals that specify a register number.
• The output signals, RdData1 and RdData2, are 32-bit signals. Their values are the contents of the register specified by the port input signal.

Write Port

The input signals, WrReg and WrData, and the control input signal WrEn make up the write port.

• WrReg specifies the register number for the register to be written.
• WrData specifies the data to be written to the register.
• WrEn enables the write when its value is 1. The write does not happen if WrEn is 0. This signal is necessary because not all instructions write to a register.

Data Memory

The Data Memory component is actually just an interface to the bus that interconnects the processor, main memory, and I/O devices. Since other devices use this bus, an enable signal is required for both memory reads and memory writes.

Note that the Address input is shared by both the read port and the write port.

Read Port

The input signal, Address, the output signal, RdData, and the control input signal RdEn make up the read port.

• The input signal Address is a 32-bit signal that specifies a memory address.
• The output signal RdData is a 32-bit signal. Its value is the data at the address specified by the Address input signal.
• RdEn enables the read when its value is 1. The write does not happen if RdEn is 0. This signal is necessary to ensure the processor does not access the bus except when it needs to.

Write Port

The input signals, Address and WrData, and the control input signal WrEn make up the write port.

• The input signal Address is a 32-bit signal that specifies a memory address.
• WrData specifies the data to be written at that address.
• WrEn enables the write when its value is 1. The write does not happen if WrEn is 0. This signal is necessary to ensure the processor does not access the bus except when it needs to.

Instruction Memory

Instruction Memory has a simple task: given a memory address input, fetch the instruction at that address. Consequently, the interface to Instruction Memory is just a single read port.

• The input signal Address is a 32-bit signal that specifies an instruction address.
• The output signal Instruction is a 32-bit signal. Its value is the instruction at the address specified by the Address input signal. For convenience, the instruction is then broken up into its fields.

Instruction Memory does not show a read enable because it is automatic — in a single-cycle implementation an instruction is read every cycle.

Reality Check

Modern processors put both instructions and data into the same memory. It is too expensive to have two separate read ports into a large memory. You can get an effect like two ports by having two separate caches — one for instructions and one for data. Modern processors usually do this to improve performance.

But if you are willing to spend money on caches to improve performance, then you would first spend a smaller amount of money converting the single-cycle implementation into a multicycle implementation. A multicycle implementation puts instruction and data access into different cycles so you only need one memory.