EE4305: Computer Architecture Lab Projects

Lab location: MWAH 41 or your home, Lab Hours: Open Lab, Lab Check-off: 1:00-4:00pm Thursday
Each student must use his or her own flash memory stick to store his/her own project files when MWAH 41 PCs are used.

Nexys4-DDR Master XDC (Xilinx Design Constraint) File .
Lab Policies
Software Version used in the lab: Xilinx Vivado HLx 2019.1 WebPack
Nexys4-DDR (=Nexys A7) Reference Manual
Nexys-4 DDR I/O Schematic (Nexys-4 board I/O Pin Maps).
Default Part and Product Family Setup .
Numeric_std conversion chart
VHDL Language Syntax (VHDL Syntax Reference).
Green Sheet MIPS Instruction set
Java SE installation instruction , required to run MARS
MWAH 41 Access (key) Request Form

(Points for labs completed passing its due date (late labs) are in general gradually reduced for more dates late up to one week, i.e., it becomes zero points after one week late.)