EE 5311 Design of VLSI Circuits

 

Instructor:                Hua Tang

Office:                      276 MWAH

Office hour:              10-11am MTWF

Email:                      htang@d.umn.edu

Phone:                     (218)726-7095

 

Course Syllabus

 

 

Please feel free to stop by the office or send me an email if you have any question regarding lecture and lab. Any other suggestion regarding lecture and lab is very welcomed.

 

 

Note:  the posted slide might have more information than what was presented in class

 

Week 1

Lecture Slide 1               Introduction to VLSI design

Lecture Slide 2               MOS transistor fabrication

(1) Please read Rabaey Chapter 1 & 2

(2) http://www.intel.com/technology/timeline.pdf

(3) http://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures

(4) http://en.wikipedia.org/wiki/Intel_Core

 

Week 2

Lecture Slide 2               MOS transistor fabrication

Lecture Slide 3               MOS transistor theory

Note: Please read Rabaey Chapter 3

 

Week 3

Lecture Slide 4               MOS Inverter I

Lecture Slide 5               MOS Inverter II

Note: Please read Rabaey Chapter 5.1-5.4

 

Week 4

Lab on Tuesday                               Lab/Homework1

Lecture Slide 6               MOS Inverter III

Note: Please read Rabaey Chapter 5.5-5.7

 

Week 5

Lab on Tuesday                               Lab/Homework1

Lecture Slide 6               MOS Inverter III

Lecture Slide 7               MOS Combinational logic I

 

Week 6

Lab on Tuesday                               Lab/Homework2

Lecture Slide 7               MOS Combinational logic I

Note: Please read Rabaey Chapter 6.2.1, 6.2.2, 6.2.3

 

Week 7

Lecture Slide 8               MOS Combinational logic II

Lecture Slide 9               MOS Combinational logic III

Lab/Homework3

Note: Please read Rabaey Chapter 6.3-6.6

 

Week 8

Lab on Tuesday                               Lab/Homework4

Lecture Slide 10             MOS Sequential logic I

Lecture Slide 11             MOS Sequential logic II

Note: Please read Rabaey Chapter 7.1-7.3

 

Week 9

Lecture Slide 12             MOS Sequential logic III

Lecture Slide 13             VLSI Design Methodologies

Note: Please read Rabaey Chapter 7.4-7.6

 

Week 10

Lecture Slide 13             VLSI Design Methodologies

Lecture Slide 14             Arithmetic Building Blocks

Note: Please read Rabaey Chapter 8 and 11

 

                                                            Final Project due 12/14 noon

                                  Divider Divider II    Decoder

 

Week 11

Lab on Tuesday             Homework 5 & 6

Lecture Slide 15             Timing Issues I

 

Week 12

Lab on Tuesday             Homework 5 & 6

Lecture Slide 16             Timing Issues II

 

Week 13

Lecture Slide 16             Timing Issues II

Lecture Slide 17             Interconnect Wires I

 

Week 14

Lab on Tuesday             Final Project